Cutting Through the Confusion with ARM Cortex-M Interrupt Priorities » Interrupt priory registers with 3 bits of priority (A), and 4 bits of priority (B)
Interrupt priory registers with 3 bits of priority (A), and 4 bits of priority (B)
Interrupt priory registers with 3 bits of priority (A), and 4 bits of priority (B)
Would appreciate if you can clarify the following statements:
NVIC_SetPriority (7, 6) – This is IRQ7 at level 6 in 3-bit level – 1 1 0 (Bit 2, 1,0 )
But this is IRQ7 at level at level 6 at 4-bit level – (0 1 1 0 (Bit 3, 2, 1 , 0)
But you are also saying if it is (7, C0), the priority will be 0 ( 1 1 0 0) – I am not following this.
Does bit 7 becomes bit 2 in 3-bit system and becomes bit 3 in 4-bit system – Thank you.